1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor device including a trench gate transistor and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2007-188084, filed Jul. 19, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been progressed shrinkage of memory cells in a semiconductor device such as a dynamic random access memory which will hereinafter be referred to as DRAM, due to development of microprocessing techniques. In general, shrinkage of a memory cell may reduce the dimensions of a transistor that constitute the memory cell. Reduction in the dimensions of a transistor may cause remarkable short channel effects of the transistor. In DRAM, shrinkage of a memory cell may reduce the channel length of a transistor that is included in the memory cell. This deteriorates the performances of the transistor, thereby deteriorating data retention and writing performances of the memory cell. For example, Japanese Unexamined Patent Application, First Publications, Nos. 9-172064, 2003-7676, 2005-243932, and 2006-66611 each address trench gate transistors with a three-dimensional channel structure. A part of a gate electrode is buried with a gate insulator in a trench groove that is formed in a semiconductor substrate.